ADIVAnet
Find and report in a graphical manner net connectivity errors before product release. With ADIVA's Virtual Netlist Checking tool, designers can simulate the manufacturing netlist test process of a finished board during the design process. This verifies electrical integrity of design data before it is released to fabrication.
NetList Compare Verifies the interconnect integrity of the manufacturing data
Extracts netlist from CAD database
GRAPHICALLY displays netlist differences and marks location back in CAD System
Finds Non-Plated Holes in library shape = open net
Reveals shorted nets that should never happen
Builds netlist from GERBER, IPC-2581, or ODB++ database
Checks for opens, shorts, and mismatched CAD data
Captures Digital Images for Network Display and Sharing
Identifies clearances that isolate split planes